Digital calipers - open the small cap - and a new way of implementing behavioral programming

Hi,

Have you ever noticed those cheap Chinese digital calipers, like these, have a 4-pin PWB connector under a small cap.

Yup, the measured length is outputted from that connector. And now you can read the value into your FPGA desing:

download from here

The thing I want you to pay attention is not the reader block (that is extra bonus), but the model itself.

In the process starting fom line 192, I used a totally new (for me) approach to avoid writing yet another boring state machine.

In the main loop, I use a variable "t" of type time, to compose a waveform for clk_int and data_int nets.

The magical keyword used is "transport", which allows you to assign a new future events onto a signal, without deleting previous assignments.

So the whole sequence (of outputting 48 bits of data and clock) is updated simultaneously (from the simulation time point of view). Here's a snippet (line 219):
  for i in 1 to 23 loop
    clk_int <= transport '0' after t;
    t := t + clock_time;
    clk_int <= transport '1' after t;
    if w2(i) = '0' then
      data_int <= transport '1' after t+output_delay;
      data_int <= transport '0' after t+output_delay+glitch_time;
    else
      data_int <= transport w2(i) after t+output_delay;
    end if;
    t := t + clock_time;
  end loop;

The variable t is updated every now and then, and all signal assignments are done with "after" suffix and utilizing "transport" model.

On line 294, two timers are launched and the wait sentence will decide when to continue:
  trig_slow <= 0, 1 after rate_slow;
  trig_fast <= 0, 1 after rate_fast;
  wait until reset_in='1' or
   (mode=normal and trig_slow=1) or (mode/=normal and trig_fast=1);
  exit when reset_in = '1';

If the reset_in is hitted by '1' during the output sequence, the model will exit the loop immediately and overwrites any waveform left on data_int and clk_int, on line 202/203:
  data_int <= 'L';
  clk_int <= 'L';

I haven't yet tried this on a real caliper and FPGA. If I happen to have some spare time during summer holiday, I'll give it a try and tell the results here.

BR, -Topi