registers - getting even better

I failed to use previous version of register builder and needed to change the design pattern a bit.

vhdl registers ver_1

Has utilized generate -syntax to decide which registers to write on each situation.

You don't need to touch on registers.vhdl to expand the design. registers_pkg.vhdl describes all the functionality of whole register set, and (in the example provided) tester_registers.vhdl decides what features to actually use. The synthesizer (Altera failed again, by generating extra registers for this example) will optimize out any unwanted feature.

In the registers_pkg.vhdl lines...

    type reg_add_enum_type is (
        add_0,
        read_only,
        write_only,
        read_write,
        lo_nibble_rw,
        realtime
    );

    constant reg_add_map: reg_add_array := (
        add_0 => 0,
        read_only => 1,
        write_only => 2,
        read_write => 3,
        lo_nibble_rw => 4,
        realtime => 5
    );


    constant reg_mask: reg_mask_array := (
        add_0 => "********",
        read_only => "zzzzRRRR",
        write_only => "WWWWWWWW",
        read_write => "********",
        lo_nibble_rw => "r---****",
        realtime => "rrrrrrrr"
    );



...describe the behaviour of register set. The first, type definition, lists user-friendly names of all registers. The number of registers is the number of entries in the type.


Second one is an array listing physical addresses (from the CPU point of view) of each register. They don't have to be successive, and can have holes in the address map.

Third one tells the wanted behaviour of each register bit:
'*' means the bit can be written and read by CPU. And the FPGA has read/write access too.
'z' means the bit can be read by CPU, and reading will reset the bit to zero. FPGA has read/write access to the bit.
'R' means the bit is read only for the CPU. FPGA has read/write acces.
'W' means the bit is write only from the CPU point of view. FPGA has read/write access.
'r' means the bit is readable by CPU, and the data is passed through the register block without any storage (D-FlipFlop) (realtime access).
'-' means the bit is not used. CPU read will always return zero, and it cannot be written to.

On the block instantiating (tester_registers.vhdl) the register:

FPGA writes to non-realtime register [*zRW] you need two lines of code (lines 35/36):
    reg_update_en(read_only) <= write_ro_in;
    reg_updates(read_only) <= data_ro_in;
In this case the register named "read_only" is updated whenever write_ro_in is '1' for 1 clock cycle. The data written is in data_ro_in.

Feeding in the realtime data (line 31):
    regs_realtime(realtime) <= realtime_in;
In this case the register named "realtime" is constantly updated with signal realtime_in.

And finally getting register values out from the block (line 33):
    test_reg_out <= regs(realtime) & regs(read_write);
Notice that whole register set (all registers) are routed out from the register block. But synthesizer will optimize out any registers that are not used. In this case "regs" holds 48 bits, only 16 of them will be synthesized. You can even feed the same signal (regs) to all your blocks needing (read) access to register values, and your block can fetch out specific values for it.

And, in this case the registers were 8-bit, but I'm sure you will find out a way to change that ;)

BR, -Topi